1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an insulating film.
2. Description of the Related Art
Conventionally, semiconductor devices represented by memories such as DRAM (Dynamic Random Access Memory) and static-RAM, and logics are formed with semiconductor elements such as resistors, capacitors and the like. In the following, a semiconductor device will be described in connection with the configuration of DRAM.
FIG. 1 is a cross-sectional view illustrating an exemplary configuration of DRAM.
As illustrated in FIG. 1, the DRAM comprises memory cell region 80 in which memory cells are formed for storing information, and peripheral circuit region 90 in which a circuit is formed for selecting an arbitrary memory cell.
Each of memory cells formed in memory cell region 80 comprises cell transistor 106 and capacitor 112. Cell transistor 106 has P-well layer 103 formed within P-type silicon substrate 101 near the surface thereof; gate electrode 111a formed on P-well layer 103 through gate insulating film 110; and drain electrode 108 and source electrode 109 formed in P-well layer 103. Capacitor 112 has upper electrode 126 which serves as a plate electrode; lower electrode 124 which serves as a storage electrode; and dielectric material 125 sandwiched between upper electrode 126 and lower electrode 124.
Source electrode 109 of cell transistor 106 is connected to lower electrode 124 of capacitor 112 through silicon plug 114a, 114b made of polysilicon into which impurities are diffused to reduce the resistance. Drain electrode 108, which is shared by cell transistor 106 and cell transistor 107, is connected to bit line 117 through silicon plug 114e. Cell transistors 106, 107, which share drain electrode 108, are electrically insulated by isolation region 105 from other cell transistors. Gate electrode 111a is reduced to gate electrode interconnection 111b which serves as an interconnection on isolation region 105.
Interlayer insulating film 113 and interlayer insulating film 121 are formed between gate electrode 111a and bit line 117, while interlayer insulating film 123 is formed between bit line 117 and capacitor 112. Upper electrode 126 of capacitor 112 has a top surface covered with interlayer insulating film 130 which is formed on interlayer insulating film 123 through interlayer insulating film 127. These interlayer insulating films ensure the insulation between respective elements for preventing elements from conducting with each other except for a desired connection.
As illustrated in FIG. 1, peripheral circuit transistor 150 is formed on P-well layer 104 within P-type silicon substrate 101 in peripheral circuit region 90. Peripheral circuit transistor 150 has a source electrode and a drain electrode connected to interconnection 152 which is formed in the same layer as bit line 117 in memory cell region 80 through tungsten plug 118 which is comprised of a laminated tungsten nitride (WN) film and tungsten (W) film. Interconnection 152 is connected to interconnection 156 formed on interlayer insulating film 130 through via plug 154 which is comprised of a laminated titanium nitride (TiN) film and W film.
In the DRAM configured as described above, a predetermined cell transistor can be turned on to write or read information into or from the cell transistor by arbitrarily selecting a bit line and a gate line through the operation of the peripheral circuit, and applying voltages to the selected bit line and gate line.
FIG. 2 is a cross-sectional view illustrating a main portion of the memory cell illustrated in FIG. 1, when viewed from a different direction.
As illustrated in FIG. 2, bit lines 117a, 117b are comprised of laminated conductive WN film 119 and W film 120. Lower electrode 124 of capacitor 112 is connected to source electrode 109 through silicon plugs 114c, 114d. For electrically insulating these two bit lines 117a, 117b from silicon plug 114c, mask nitride film 158 made of a silicon nitride film (hereinafter simply called the “nitride film”) is formed on bit lines 117a, 117b, and spacer nitride film 160 is formed on side walls of bit lines 117a, 117b. 
Conventionally, spacer nitride film 160 mentioned above has been formed of a nitride film which is deposited by reacting dichlorosilane SiH2Cl2 with ammonia (NH3) at temperature of 760° C. in accordance with a CVD (Chemical Vapor Deposition) method. In the following description, dichlorosilane is designated by DCS.
For increasing the integration degree of semiconductor devices, it is necessary to further suppress diffusion of impurities within a semiconductor substrate. For suppressing the diffusion of impurities, the semiconductor substrate should undergo a reduced amount of heat treatment. For this reason, a single wafer system, which forms a nitride film on a semiconductor substrate one by one, has been prevalently used to form nitride films instead of a batch processing system which is capable of forming nitride films on a plurality of semiconductor substrates at a time, because the single wafer system applies a reduced amount of heat treatment to semiconductor substrates.
On the other hand, for reducing the amount of heat treatment in the batch processing system without using the single wafer system, there is a method for depositing a nitride film at lower temperatures. However, when a nitride film is deposited using DCS at a temperature reduced to as low as 600° C., the deposition rate becomes lower, resulting in a low throughput which represents the amount of processing per unit time.
To solve the problem of low throughput, in recent years, the deposition has been performed by a batch processing system using a reaction gas which consists of hexachlorodisilane Si2Cl6 that is capable of depositing a nitride film at temperatures lower than is capable with DCS. Such a method is disclosed in Japanese Patent Laid-open Publication No.343793/2002. In the following description, hexachlorodisilane is designated by HCD.
Nitride films were deposited using HCD under the following processing conditions: at temperature of 600° C., at a gas flow ratio HCD/NH3 equal to 1:30, for a deposition time of approximately one hour. In the following description, a nitride film formed using DCS is designated by DCS-Si3N4, and a nitride film formed using HCD is designated by HCD-Si3N4.
From the fact that the deposition of HCD-Si3N4 at approximately 600° C. entails a deposition rate equivalent to that in deposition of DCS-Si3N4 at approximately 760° C., this deposition provides a higher throughput than deposition of DCS-Si3N4 at 600° C. Also, HCD-Si3N4 deposited by a batch processing system exhibits a better coverage to an underlying step, as compared with DCS-Si3N4 deposited by a single wafer system, and is formed in a uniform thickness independently of the density of an underlying pattern. It has thus been found that HCD-Si3N4 deposited by a batch processing system is superior to DCS-Si3N4 deposited by a single wafer system in regard to the step coverage and pattern density dependence.
In a screening test made for prototype DRAMs which included a spacer nitride film made of the aforementioned HCD-Si3N4, reliability failures were found. Presumably, the failures were caused by a leak current between the silicon plug and bit line shown in FIG. 2 which was larger than a leak current of DRAM which employed DCS-Si3N4 for a spacer nitride film. To address the reliability failures, the leak current characteristic was evaluated in the following manner.
TEG (Test Element Group) used for measuring a leak current has an insulating film, subjected to the measurement of the leak current, sandwiched between two flat conductors having a predetermined pattern thereon. The measurement was made under the condition that the leak current was defined as a current flowing through the insulating film when a voltage was applied across the conductors to generate an electric field of 4 [MV/cm] across the conductors.
It was found from the result of the measurement that HCD-Si3N4 exhibited a leak current of approximately 3E-4 [A/cm2] which was larger by approximately three orders of magnitude than a leak current of approximately 2E-7 [A/cm2] exhibited by DCS-Si3N4. When a large leak current flows from a lower electrode of a capacitor of a DRAM into a bit line through a silicon plug, the capacitor can store charges for a shorter time, so that the DRAM must be refreshed at shorter time intervals, resulting in larger power consumption of the DRAM.
Next, for evaluating DRAMs in a structure similar to actual products, a burn-in test was conducted for the structure illustrated in FIG. 2, wherein a high voltage was applied between the silicon plug and bit line at high temperatures to acceleratively apply a load on the insulating film. The result of the burn-in test will be described below.
FIG. 3 is a graph showing the convergence of percent defective resulting from the burn-in test made for DCS-Si3N4 and HCD-Si3N4. The horizontal axis represents the number of times of the burn-in test which took a duration λ each time, and the vertical axis represents the percent defective.
As shown in FIG. 3, DCS-Si3N4 required five tests before the percent defective was reduced to 200 fit, which was defined to be a product shipment reference, or less, whereas the percent defective associated with HCD-Si3N4 was higher than 200 fit and did not converge even after the test had been conducted seven times. From the foregoing result, a semiconductor device which employs a spacer nitride film made of a single layer of HCD-Si3N4 will entail an increased number of steps for screening, as compared with a semiconductor device which employs a spacer nitride film made of a single layer of DCS-Si3N4, thereby possibly increasing a period from the start of manufacturing to shipment of the semiconductor devices as well as the cost of the semiconductor devices.